1. Technical Field
The present invention relates generally to integrated circuit test circuits, and more specifically to an on-wafer dedicated measurement data pre-processor circuit.
2. Description of the Related Art
Semiconductor circuit speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. As existing technologies are pushed to their limits, yield and performance analyses and testing become ever more necessary for semiconductor die circuit designs.
Historically, circuit designs have been simulated using programs that predict the performance of the circuits over environmental and process variations. More recently, test circuits have been incorporated either on the die or on the kerf that provide useful information about circuit performance over environmental and process variations. A common circuit that is implemented for testing circuit delays is a ring counter that oscillates at a frequency dependent on the total circuit delay around the ring. Other circuits may be implemented to determine transition times, and other process/environment dependent performance variables.
The output of the above-described circuits is commonly measured with a tester that extracts the needed measurement data from the circuit and performs analytical computation on the extracted measurement data. Typically, a statistical analysis is performed that predicts yield/performance behavior of a given circuit and process. The statistical computations are both input data-intensive and computation intensive.
The bandwidth of the typical tester-wafer connection is limited to approximately 100 Mhz, while present circuits are operating at frequencies approaching 5 Ghz and beyond. If some pre-processing reduction of the measurement data could be performed, the resulting improvement of test and analysis speed would decrease the turn-around time of the measurement and analysis process and/or make it possible to perform deeper analyses in the same time period. However, any data reduction can limit the possible value of the statistical analysis, as each measurement taken is generally relevant to the statistics of each performance variable.
It would therefore be desirable to provide a method and apparatus that reduces measurement/analysis time for process and environment-dependent performance variable wafer tests. It would further be desirable to provide a method and apparatus compatible with currently used statistical techniques, so that no effective loss of analysis input occurs due to the reduction in measurement/analysis time.